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Energy optimization of pipelined digital systems using circuit sizing and supply scaling

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3 Author(s)
H. Q. Dao ; Electr. & Comput. Eng. Dept., Univ. of California, Davis, CA, USA ; B. R. Zeydel ; V. G. Oklobdzija

We present a systematic method for minimizing the energy of pipelined digital systems, through joint optimization of each pipeline stage and the system. A pipeline stage with a constant load can either be optimized for delay at a given input size, minimized for energy at a fixed delay, or have delay traded off for energy at a fixed input size. The results of these optimizations are combined to yield the design region for energy and delay. At the system level with a fixed throughput constraint, the sensitivities to input size and output load of all pipeline stages form the optimal energy criteria that provide a systematic method to minimize the total system energy. This method is applied to a media datapath, where we show up to 37% energy saving for a fixed performance. The minimal energy-delay curve of the system obtained through application of this method demonstrates similar characteristics as that of a single pipeline stage. With voltage scaling, the optimal solution displays a strong dependency between delay, energy, and supply voltage. The proper tradeoff between these entities makes a fundamental impact on efficient digital design.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:14 ,  Issue: 2 )