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A two-stage amplifier, operational at 0.8V and drawing 7μA, has been integrated in a standard digital 0.18μm CMOS process. Rail-to-rail operations at the input are enabled by complementary transistor pairs with gm control. The efficient rail-to-rail output stage is biased in class AB. The measured DC gain of the amplifier is 75dB, and the unity-gain frequency is 870kHz with a 12pF, 100kΩload. Both input and output stage transistors are biased in weak inversion.