By Topic

An ultra-low energy asynchronous processor for wireless sensor networks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Necchi, L. ; Politecnico di Torino ; Lavagno, L. ; Pandini, D. ; Vanzago, L.

This paper describes the design flow used for an asynchronous 8-bit processor implementing the Atmel AVR instruction set architecture. The goal is to show dramatic reductions in power and energy with respect to the synchronous case, while retaining essentially a traditional design flow. The processor was implemented in a 130nm technology using desynchronization, starting from an initial design downloaded from It consumes 14 pJ per instruction to deliver 170 MIPS at 1.2 V, and 2.7 pJ per instruction to deliver 48 MIPS at 0.54 V. It thus dramatically improves the energy consumed per instruction with respect to previous results from the literature

Published in:

Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on

Date of Conference:

13-15 March 2006