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Acceleration of Modular Exponentiation on System-on-a-Programmable-Chip

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4 Author(s)
P. Hamalainen ; Institute of Digital and Computer Systems Tampere University of Technology Tampere, Finland ; Ning Liu ; M. Hannikainen ; T. D. Hamalainen

Computing modular exponentiations with long integers is required in a number of security protocols. Since security procedures typically consume large amount of processing capacity in network devices, efficient implementations are needed. As a solution, this paper presents an exponentiation accelerator suited for efficient processing in security protocols using public key schemes, such as TLS and IPsec. The accelerator is implemented on a system-on-a-programmable-chip, partitioned into software control and hardware processing. Compared to previous radix-2 designs, significantly higher performance is achieved. The design computes a full exponentiation in (n+k)(n+4) clock cycles, in which n is the bit length of the modulus and the exponent and k is the number of ones in the binary representation of the exponent. In the average case, the design executes the exponentiation 25% faster than the previous hardware designs at equal clock speeds. The proposed exponentiation control and 1-cycle processing mode can also be utilized for improving higher radix designs.

Published in:

2005 International Symposium on System-on-Chip

Date of Conference:

17-17 Nov. 2005