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On Fault Detection in CMOS Logic Networks

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2 Author(s)
Kuang-Wei Chiang ; Department of Electrical Engineering University of Ottawa ; Vranesic, Z.G.

This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.

Published in:

Design Automation, 1983. 20th Conference on

Date of Conference:

27-29 June 1983

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