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Layout System for the Random Logic Portion of MOS LSI

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5 Author(s)
I. Shirakawa ; Osaka University, Osaka, Japan ; N. Okuda ; T. Harada ; S. Tanu
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The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on the basis of a set of optimization heuristics. Experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.

Published in:

Design Automation, 1980. 17th Conference on

Date of Conference:

23-25 June 1980