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Empirical observations are used to derive analytic formulae for test volumes, parallel fault simulation costs, deductive fault simulation costs, and minimum test pattern generation costs for LSSD logic structures. The formulae are significant in projecting growth trends for test volumes and various test generation costs with increasing gate count G. Empirical data is presented to support the thesis that test volume grows linearly with G for LSSD structures that cannot be partitioned into disjoint substructures. Such LSSD structures are referred to as "coupled" structures. Based on empirical observation that the number of latches in an LSSD logic structure is proportional to the gate count G, it is shown that the logic test time for coupled structures grows as G2. It is also shown that (i) parallel fault simulation costs grow as G3 (ii) deductive fault simulation costs grow as G2, and (iii) the minimum test pattern generation costs grow as G2. Based on these projections some future testing problems become apparent.