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Process and temperature compensation in a 7-MHz CMOS clock oscillator

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3 Author(s)
Sundaresan, K. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Allen, P.E. ; Ayazi, F.

This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25-μm, two-poly five-metal (2P5M) CMOS process. Measurements made across a temperature range of -40°C to 125°C and 94 samples collected over four fabrication runs indicate a worst case combined variation of ±2.6% (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95% of the samples were found to fall within ±0.5% of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was ±0.31% for a supply voltage range of 2.4-2.75 V. The clock generator is based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with temperature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is developed. The biasing circuit changes the control voltage of the differential ring oscillator to maintain a constant frequency. A comparator included at the output stage ensures rail-to-rail swing. The oscillator is intended to serve as a start-up clock for micro-controller applications.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 2 )

Date of Publication:

Feb. 2006

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