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A 14-bit analog-to-digital converter (ADC) design for GSM/GPRS/EDGE handsets is implemented in 0.25 μm CMOS. The measured SNR/SNDR/DR is 85.2/84.1/88 dB respectively. The modulator and the clock generator consume 1.05 mA from 2.7 V supply. A delay-locked-loop (DLL)-based bias scheme is implemented to guarantee that amplifier slewing takes a fixed percentage of the clock cycle over process corners, temperature, and clock frequency. The proposed biasing scheme is shown to minimize settling error variations and contain design margins.