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A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets

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2 Author(s)
Klemmer, N. ; Ericsson Mobile Platforms, Research Triangle Park, NC, USA ; Hegazi, E.

A 14-bit analog-to-digital converter (ADC) design for GSM/GPRS/EDGE handsets is implemented in 0.25 μm CMOS. The measured SNR/SNDR/DR is 85.2/84.1/88 dB respectively. The modulator and the clock generator consume 1.05 mA from 2.7 V supply. A delay-locked-loop (DLL)-based bias scheme is implemented to guarantee that amplifier slewing takes a fixed percentage of the clock cycle over process corners, temperature, and clock frequency. The proposed biasing scheme is shown to minimize settling error variations and contain design margins.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 2 )

Date of Publication:

Feb. 2006

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