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PVT-aware leakage reduction for on-die caches with improved read stability

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4 Author(s)
Jae-Joon Kim ; Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA ; Jae-Joon Kim ; Ik-Joon Chang ; Roy, K.

Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-μm 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 1 )