Referenced Items are not available for this document.
The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-μm CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
1
)
Date of Publication: Jan. 2006
- Page(s):
- 122 - 126
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8710507
- Digital Object Identifier :
- 10.1109/JSSC.2005.859016
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 27 December 2005
- Issue Date :
- Jan. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
