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The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-μm CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.
Date of Publication: Jan. 2006