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A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications

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7 Author(s)
K. Takeda ; Syst. Devices Res. Labs., NEC Corp., Kanagawa, Japan ; Y. Hagihara ; Y. Aimoto ; M. Nomura
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To help overcome limits to the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. For the same speed, the area of our proposed SRAM is 23% smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM macro using 90-nm CMOS technology and have obtained with it a minimum VDD of 440 mV and a 20-ns access time with a 0.5-V supply.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 1 )