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A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM

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4 Author(s)
A. M. Cofler ; STMicroelectronics, Grenoble, France ; F. Druilhe ; D. Dutoit ; M. Harrand

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware accelerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit embedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solution). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 × 12 ball-grid array. Full chip standby mode current is 690 μA (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 1 )