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Compiler-guided leakage optimization for banked scratch-pad memories

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4 Author(s)
Kandemir, M. ; Comput. Sci. & Eng. Dept., Pennsylvania State Univ., University Park, PA, USA ; Irwin, M.J. ; Guilin Chen ; Kolcu, I.

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:13 ,  Issue: 10 )

Date of Publication:

Oct. 2005

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