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A statistical study of the effectiveness of BIST jitter measurement techniques

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3 Author(s)
D. Bordoley ; Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA ; H. Nguyen ; M. Soma

This paper describes a statistical study of the effectiveness of state-of-the-art built-in-self-test (BIST) jitter measurement techniques. Many BIST solutions under-sample the signal under test, estimating the jitter in a system based upon a subset of the total number of clock edges. In this paper, we explore how under-sampling affects the accuracy of jitter measurements, and demonstrate a technique for estimating the actual jitter using a Gaussian distribution estimation. Our theoretical results were verified through a simulation study and comparison to experimental data collected from a 400 MHz phase-locked loop supplied by an industry sponsor.

Published in:

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

Date of Conference:

6-10 Nov. 2005