By Topic

A 0.18 μm CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

A high-speed CMOS encoder intended for a 5 gigasample/second (GS/s) 4-bit flash analogue-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signalling is used in all the internal sub-blocks of the ADC, including the encoder, which is implemented in current-mode logic (CML). To further enhance the encoders speed, two-stage pipelining is used. Details of the architecture are described. The proposed two-stage pipelined encoder as well as an encoder with no pipelining are designed and simulated in a 0.18 µm CMOS technology, and their performances are compared. Simulation results predict a 40% speed improvement for the pipelined encoder. The encoder circuit consumes 4 mW from a 1.8 V supply while operating at 5 GHz.

Published in:

Canadian Journal of Electrical and Computer Engineering  (Volume:30 ,  Issue: 4 )