By Topic

A 10mW 81dB cascaded multibit quadrature ΣΔ ADC with a dynamic element matching scheme

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
R. Maurino ; Analog Devices, Berkshire, UK ; C. Papavassiliou

A multibit 2-0 cascaded quadrature ΣΔ modulator is presented which attains 81 dB dynamic range in a 200kHz bandwidth at an IF of 10MHz. A simple dynamic element matching (DEM) scheme minimizes the mirror in-band aliases caused by mismatch between the I and Q channel. The integral nonlinearity (INL) errors from the multibit feedback DAC are noise-shaped by a quadrature variant of the data weighted averaging algorithm (DWA). Clocked at 13.1 MHz, the ADC consumes 10mW from a 2.1 V supply.

Published in:

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

Date of Conference:

12-16 Sept. 2005