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A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology

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4 Author(s)
Tajalli, A. ; Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran ; Muller, P. ; Atarodi, M. ; Leblebici, Y.

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18μm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/ch and each channel occupies 0.045μm2 silicon area.

Published in:

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Date of Conference:

12-16 Sept. 2005

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