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Scan testing is expensive in power consumption as each test vector requires a large number of shift operations with a high circuit activity. For a scan cell, the number of transitions caused by a test vector being scanned in depends not only on the transitions in the test vector but also on its position in the scan chain. Depending on the circuit structure, the transitions at some scan cells may cause more transitions at the internal circuit than those at other scan cells. Therefore, reducing scan transitions at those scan cells that cause more transitions in the internal circuit will result in greater reduction in switching activity. In the paper, the authors propose a scan cell ordering approach to reduce scan power consumption by arranging the scan cells which cause more internal circuit transitions to the positions with low transition weights in the scan chain. Two functions are developed to compute the transition weight of a scan cell and to measure the impact of transitions at a scan cell on switching activity in the internal circuit, respectively. Experiments performed on the ISCAS 89 benchmark circuits show that the average power consumption during scan testing can be reduced up to 17.35%. Moreover, because the proposed approach is independent of the order of test vectors, it can be utilised together with the existing test vector reordering techniques to further reduce test power.
Computers and Digital Techniques, IEE Proceedings - (Volume:152 , Issue: 5 )
Date of Publication: 9 Sept. 2005