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An accurate physical model of switched-capacitor ΔΣ analog-to-digital converters (ADCs) noise is presented. Noise artifacts for various ADC blocks are captured using simple equations. Model is verified against measured 0.25-μm high dynamic range ADC test chip for a wireless receiver. Design guidelines based on the proposed model are discussed.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:52 , Issue: 11 )
Date of Publication: Nov. 2005