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Plated through via (PTV) structures are widely used in printed circuit boards for interconnect. Due to the mismatch in the coefficient of thermal expansion (CTE) between the PTV and the board material, high thermal stresses can be induced in the PTV during high temperature soldering and normal usage. In particular, PTVs can fail due to cyclic temperature changes which cause thermal fatigue. This paper describes an analytical model of the thermal stresses in PTV structures using variational mechanics. Stress components are compared with those obtained using finite element analysis and with another analytical model.