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Linear programming for sizing, Vth and Vdd assignment

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2 Author(s)
Chinnery, D.G. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Keutzer, K.

Most circuit sizing tools calculate the tradeoff between each gate's delay and power or area, and then greedily change the gate with the best tradeoff. We show this is suboptimal. Instead we use a linear program to minimize circuit power. The linear program provides a fast and simultaneous analysis of how each gate affects gates it has a path to. Our approach reduces power by up to 30% compared to commercial software, with a 0.13μm library. The runtime for posing and solving the linear program scales linearly with circuit size.

Published in:
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

Date of Conference: 8-10 Aug. 2005

Page(s):
149 - 154
Print ISBN:
1-59593-137-6
INSPEC Accession Number:
8688811
Digital Object Identifier :
10.1109/LPE.2005.195505
Product Type:
Conference Publications

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