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This paper discusses a number of circuit techniques which address the DC and AC distortion performance of a low power current steering digital-to-analog converter design. The design provides 14 bit resolution and 200 MSPS conversion rate in a 1P4M 0.18 micron CMOS process, with optional 3.3 volt compatible devices, while operating over a wide 3.6 to 1.8 volt supply range. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8V operation and as low as 0.28 mW/MSPS at 3.3V. SFDR of 70 dB is achieved at a 50 MHz output frequency.