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We present a computation reduction technique called computation sharing differential coefficient (CSDC) method, which can be used to obtain low-complexity multiplierless implementation of finite-impulse response (FIR) filters. It is also applicable to digital signal processing tasks involving multiplications with a set of constants. The main component of our proposed CSDC method is to combine the strength of the augmented differential coefficient approach and subexpression sharing. Exploring computation reuse through algorithmic equivalence, the augmented differential coefficient approach greatly expands the design space by employing both differences and sums of filter coefficients. The expanded design space is represented by an undirected and complete graph. The problem of minimizing the adder cost (the number of additions/subtractions) for a given filter is transformed into a problem of searching for an appropriate subexpression set that leads to a minimal adder cost. A heuristic search algorithm based on genetic algorithm is developed to search for low-complexity solutions over the expanded design space in conjunction with exploring subexpression sharing. It is shown that up to 70.1% reduction in the adder cost can be obtained over the conventional multiplierless implementation. Comparison with several existing techniques based on the available data shows that our method yields comparable results for multiplierless FIR filter implementation.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:52 , Issue: 9 )
Date of Publication: Sept. 2005