Referenced Items are not available for this document.
A backplane transceiver core in 0.13 μm dual-gate CMOS, operating at 0.6 to 9.6 Gb/s with an area of 0.56 mm2 and dissipating 150 mW at 6.25 Gb/s, is presented. This core uses a unique adaptive receive equalization strategy, transmit pre-emphasis, and has extensive optional test features including a built-in BER tester and an on-chip receiver sampling scope.
Published in:
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Date of Conference: 10-10 Feb. 2005
- Page(s):
- 64 - 585 Vol. 1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-8904-2
- INSPEC Accession Number:
- 8643460
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2005.1493870
- Product Type:
- Conference Publications
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