The proposed 5Gb/s transceiver has a transmitter with 2-tap pre-emphasis and an adaptive receiver with 1-tap feedforward and 3-tap decision feedback equalization. The quad transceiver occupies 12 mm2 in 0.13 μm CMOS, consumes 2.1 W from 1.2 V, and has a BER<10-15 over 4 pairs of 1-meter backplane trace with crosstalk.
Published in:
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Date of Conference: 10-10 Feb. 2005