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Optimization for Chip Stack in 3-D Packaging

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9 Author(s)
K. Hara ; Adv. Technol. Dev. Dept., Seiko Epson Corp., Nagano, Japan ; Y. Kurashima ; N. Hashimoto ; K. Matsui
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We have been developing three-dimensional (3-D) packaging technology for forming through-type electrodes in chips that are then directly connected in stacks. The model examined in this study is defined by its simple structure. The structure was optimized for successful connection in a chip stack without degrading the features of the chips. The use of this structure enabled a stable and rigid connection, and a four-layer chip stack assembled on a ceramic substrate exhibited adequate thermal cycle performance. This paper discusses how the structure of terminals was optimized for chip stacking. A finished package assembled from static random access memory (SRAM) with through-type electrodes was confirmed to operate well and exhibit normal functioning.

Published in:

IEEE Transactions on Advanced Packaging  (Volume:28 ,  Issue: 3 )