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Output Impedance Design of Parallel-Connected UPS Inverters With Wireless Load-Sharing Control

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5 Author(s)
J. M. Guerrero ; Dept. d'Enginyeria de Sistemes, Escola Univ. d'Enginyeria Tecnica Ind. de Barcelona, Spain ; Luis Garcia de Vicuna ; J. Matas ; M. Castilla
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This paper deals with the design of the output impedance of uninterruptible power system (UPS) inverters with parallel-connection capability. In order to avoid the need for any communication among modules, the power-sharing control loops are based on the P/Q droop method. Since in these systems the power-sharing accuracy is highly sensitive to the inverters output impedance, novel control loops to achieve both stable output impedance and proper power balance are proposed. In this sense, a novel wireless controller is designed by using three nested loops: 1) the inner loop is performed by using feedback linearization control techniques, providing a good quality output voltage waveform; 2) the intermediate loop enforces the output impedance of the inverter, achieving good harmonic power sharing while maintaining low output voltage total harmonic distortion; and 3) the outer loop calculates the output active and reactive powers and adjusts the output impedance value and the output voltage frequency during the load transients, obtaining excellent power sharing without deviations in either the frequency or the amplitude of the output voltage. Simulation and experimental results are reported from a parallel-connected UPS system sharing linear and nonlinear loads.

Published in:

IEEE Transactions on Industrial Electronics  (Volume:52 ,  Issue: 4 )