Cart (Loading....) | Create Account
Close category search window
 

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-μm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Rana, R.S. ; Integrated Circuits & Syst. Lab., Inst. of Microelectron., Singapore

The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-μm CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm2. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 8 )

Date of Publication:

Aug. 2005

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.