By Topic

Hi-CMOS III technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)

Hi-CMOS III (1.3µm CMOS) technology is described. The basic approach is the 2/3 scaling of Hi-CMOS II (2µm CMOS) with constant voltage. Lightly Doped Drain (LDD) NMOS, and newly developed Buried Channel Lightly Doped Drain (BCLDD) PMOS, with polycide gate are adopted to reduce short channel effects and delays in interconnection lines. Both NMOS and PMOS can be used at the gate length of 1.2µm. Spacers for LDD and tapered contact holes have improved the coverage of aluminum layer significantly. Also post-contact-doping is adopted to allow the overlap of contact holes and diffusion edges, and to reduce contact resistance. These process integration result in simple and high performance Hi-CMOS III technology.

Published in:

Electron Devices Meeting, 1984 International  (Volume:30 )

Date of Conference: