A merged CMOS/bipolar VLSI process

Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series resistance and CMOS transistors. Latch-up suppression and effective bipolar performance are simultaneously achieved by the combined use of an n+ buried layer, epitaxial processing and a tailored base ion implant. A merged CMOS/bipolar buffer circuit is described and measured results are shown.