Application of low pressure silicon epitaxy to subnanosecond bipolar logic LSIS

Low-pressure silicon epitaxial technology is applied to high-speed bipolar logic LSIs to reduce autodoping from heavily-doped substrates. As a result, collector-base stray-capacitance (C
Tc
) is remarkably reduced. In this report, the dependence of CTC on epi-layer thickness and the C
TC
dependence of t
pd
(propagation delay time) are also mentioned. The propagation delay time, t
pd
is reduced by about 10-15% due to the reduction of C
TC
caused by applying low pressure epitaxy. The obtained minimum value of t
pd
is about 0.35 ns.