Referenced Items are not available for this document.
This paper describes a 3 volt partial analog adaptive equalizer that is intended to be used with a digital decision feedback equalizer (DFE). The analog filter was realized in a 0.5µm CMOS process and has a bandwidth of 100MHz while consuming 23mW of power. It has one tuning parameter and eliminates precursor intersymbol interference in a 311 Mbits/second system encoded as a 4-level PAM signal over 0 to 300 meters of coaxial cable.
Published in:
Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European
Date of Conference: 21-23 Sept. 1999
- Page(s):
- 42 - 45
- Conference Location :
- Duisburg, Germany
- Product Type:
- Conference Publications
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