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4.0GHz 0.18μm CMOS PLL based on an interpolate oscillator

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5 Author(s)
F. H. Gebara ; Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA ; J. D. Schaub ; A. J. Drake ; K. J. Nowka
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Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which is capable of clocking even the most demanding logic families. Experimental results, from a TSMC 0.18μm process, show oscillator frequencies as high as 4.6GHz and rms jitter values of less then 1.25ps. Additionally, the PLL was able to lock to form a 4GHz output signal. These results are among the best published to date in this process.

Published in:

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

Date of Conference:

16-18 June 2005