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A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

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4 Author(s)
Weining Ni ; Inst. of Semicond., Chinese Acad. of Sci., China ; F. F. Dai ; Yin Shi ; R. C. Jaeger

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q2 random walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35μm CMOS technology with core area of 1.11 mm2.

Published in:

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

Date of Conference:

16-18 June 2005