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A DLL-based frequency multiplier for MBOA-UWB system

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2 Author(s)
Tai-Cheng Lee ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Keng-Jan Hsiao

A delay-locked loop (DLL)-based frequency multiplier is designed for the ultrawideband (UWB) mode-1 system. This clock generator with 528-MHz input reference frequency can achieve less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. The UWB clock generator has been fabricated in a 0.18-μm CMOS process and consumes only 54 mW from a 1.8-V supply while exhibiting a sideband magnitude of -35.3 dB and -94 dBc/Hz phase noise at the frequency offset of 50 kHz.

Published in:

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

16-18 June 2005