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A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor

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12 Author(s)
Hwa-Joon Oh ; IBM Syst. & Technol. Group, Austin, TX, USA ; Mueller, S.M. ; Jacobi, C. ; Tran, K.D.
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The floating point unit in the synergistic processor element of a CELL processor is a fully-pipelined 4-way SIMD unit designed to accelerate media and data streaming. It supports 32-bit single-precision floating point and 16-bit integer operands with two different latencies, optimizing the performance of critical single-precision multiply-add operations. It employs fine-grained clock gating for power saving. Architecture, logic, circuits and integration are co-designed to meet the performance, power, and area goals.

Published in:

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Date of Conference:

16-18 June 2005