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A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure

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6 Author(s)
Itoh, N. ; Renesas Technol. Corp., LSI Technol. Unit, Hyogo, Japan ; Tsukamoto, Y. ; Shibagaki, T. ; Nii, K.
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We introduce the advanced rectangular styled Wallace-tree construction method. This method realizes a compact layout and high-speed operation of multiplier. A 32×24-bit multiplier-accumulator was constructed using this new method. 540 um×840 um area size and 300 MHz clock speed were achieved using 0.15 um CMOS logic process technology with flash memory.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005