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A novel, low-power, reconfigurable FFT processor is proposed. The architecture is served as a scalable IP core which is suitable for system-on-chip applications. The system can be configured as 16-point to 1024-point FFT. Flexibility is added to address the generation block, coefficient memory block and data memory block. Two switch blocks are implemented to route data and addresses to the right memory blocks. Compared with a conventional ASIC FFT processor, this FFT processor is characterized by having reconfigurability; compared with an FFT processor which is mapped onto a general purpose reconfigurable architecture, it has lower-power and smaller area consumption.