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High level hardware/software communication estimation in shared memory architecture

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4 Author(s)
Pandey, Sujan ; Inst. of Microelectron. Syst., Darmstadt, Germany ; Zimmer, H. ; Glesner, M. ; Muhlhauser, M.

The paper presents a method of modeling on-chip communication behavior of a system as a set of communicating processes to find an optimal bus width and interface buffer size for the communication bus. An assumption for the modeling is that the system has already been partitioned and mapped onto the appropriate components of an SoC. We parameterize the communication behavior of a mixed Hw/Sw system considering the amount of data to be transferred, on-chip bus width, computation time of synthesized hardwares, bus topology and bus protocol. With these parameters, we estimate the transition probabilities between the communicating processes and model the overall communication behavior of a system by a Markov chain. This model is used to estimate the round trip communication delay and buffer size in the bus-interfaces for different bus widths. From the estimated figures, we select the optimal values for those parameters that satisfy given design constraints. The results of applying this approach to an Ogg Vorbis decoder clearly demonstrate the utility of our techniques for modeling communication behavior in order to estimate the bus width and buffer requirements of a complex system.

Published in:

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Date of Conference:

23-26 May 2005

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