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On-chip hermetic packaging enabled by post-deposition electrochemical etching of polysilicon

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2 Author(s)
Rihui He ; Dept. of Mech. & Aerosp. Eng., Los Angeles California Univ., CA, USA ; Chang-Jin Kim

The authors present a novel monolithic on-wafer packaging, which solves the main problems of existing monolithic encapsulation techniques for MEMS polysilicon surface micromachining. It involves the formation of a nanoporous polysilicon encapsulation layer by post-deposition electrochemical etching on top of PSG sacrificial layer, followed by removal of the sacrificial layer through the nanopores and a final vacuum sealing by depositing a polysilicon layer. Thanks to the nanopores through the thick porous polysilicon layer, the vacuum sealing is achieved by depositing a polysilicon layer as thin as 1000 Å, and no sealing material is deposited inside the cavity. The pressure inside the sealed cavity, measured by an encapsulated polysilicon pirani gauge, was around 200 mTorr and showed no detectable leaks over 3 months.

Published in:

Micro Electro Mechanical Systems, 2005. MEMS 2005. 18th IEEE International Conference on

Date of Conference:

30 Jan.-3 Feb. 2005