Referenced Items are not available for this document.
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. This is an entirely new implementation of the Sparc V9 architectural specification, which exploits large amounts of on-chip parallelism to provide high throughput. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar, level-2 cache, and memory controllers for a highly integrated design that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.
Published in:
Micro, IEEE
(Volume:25
,
Issue:
2
)
Date of Publication: March-April 2005
- Page(s):
- 21 - 29
- ISSN :
- 0272-1732
- INSPEC Accession Number:
- 8403428
- Digital Object Identifier :
- 10.1109/MM.2005.35
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 20 June 2005
- Issue Date :
- March-April 2005
- Sponsored by :
- IEEE Computer Society
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