A universal architecture for designing efficient modulo 2ⁿ+1 multipliers

This paper proposes a simple and universal architecture for designing efficient modified Booth multipliers modulo (2ⁿ+1). The proposed architecture is comprehensive, providing modulo (2ⁿ+1) multipliers with similar performance and cost both for the ordinary and for the diminished-1 number representations. The performance and the efficiency of the proposed multipliers are evaluated and compared with the earlier fastest modulo (2ⁿ+1) multipliers, based on a simple gate-count and gate-delay model and on experimental results obtained from CMOS implementations. These results show that the proposed approach leads on average to approximately 10% faster multipliers than the fastest known structures for the diminished-1 representation based on the modified Booth recoding. Moreover, they also show that the proposed architecture is the only one taking advantage of this recoding to obtain faster multipliers with a significant reduction in hardware. With the used figures of merit, the proposed diminished-1 multipliers are on average 10% and 25% more efficient than the known most efficient modulo (2ⁿ+1) multipliers for Booth recoded and nonrecoded multipliers, respectively.