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A software approach to fault detection on programmable systolic arrays

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2 Author(s)
R. Hughey ; Dept. of Comput. Sci., Brown Univ., Providence, RI, USA ; D. P. Lopresti

Current approaches to fault detection on processor arrays can be classified as hardware-based or algorithmic. The former are particularly rigid while the latter are restricted in their application. The paper presents two versions of general-purpose software fault detection for programmable systolic arrays. The methods automatically transform cell programs to provide fault detection, allowing the user more flexibility than hardware methods and more generality than algorithmic methods. Additionally, since they are based in software, the fault detection can easily be eliminated when ether methods are more appropriate

Published in:

Parallel and Distributed Processing, 1990. Proceedings of the Second IEEE Symposium on

Date of Conference:

9-13 Dec 1990