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From packaging to fast timing simulators

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1 Author(s)
Goknar, C. ; ECE Dept., Dogus Univ., Istanbul, Turkey

When considering all the steps from packaging to verification of the design one is faced with many challenges ranging from the choice of the proper tools to model the device/interconnect physics, to high level simulations at the timing level. This paper starts by reviewing some of the tools available for extraction of device/interconnect parameters from their structure and shows how they are put to use in high level simulators such as ILLIADS-I.

Published in:

Electromagnetic Compatibility, 2003. EMC '03. 2003 IEEE International Symposium on  (Volume:2 )

Date of Conference:

11-16 May 2003