Referenced Items are not available for this document.
A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-μm three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42μm2 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm2 and features a ×16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:40
,
Issue:
4
)
Date of Publication: April 2005
- Page(s):
- 902 - 908
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8397744
- Digital Object Identifier :
- 10.1109/JSSC.2004.842856
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 25 April 2005
- Issue Date :
- April 2005
- Sponsored by :
- IEEE Solid-State Circuits Society
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