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A low-voltage CMOS switch with a novel clock boosting scheme

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1 Author(s)
M. Keskin ; Mixed-Signal Design Group, Qualcomm Inc., San Diego, CA, USA

There is a strong demand for an input switch in switched-capacitor circuits, covering rail-to-rail signal swing when low power-supply voltages are used. This brief proposes a novel clock-boosting scheme. The generated clock voltages of this new circuit are applied to a regular CMOS transmission gate to implement a simple and robust sampling switch when the supply voltages are very low. In this new approach, during the sampling phase, the gate-voltage of an nMOS switch is boosted up to Vdd+k·Vdd, and the gate voltage of a pMOS switch is lowered to Vgnd-k·Vdd, where k can be made programmable, and is usually smaller than 1. This allows sampling of the full signal swing, even when supply voltages are lower than |Vth,p|+Vth,n without applying extreme stress to the gate oxide of a transistor.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:52 ,  Issue: 4 )