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A parametrizable low-power high-throughput turbo-decoder

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3 Author(s)
Prescher, G. ; Chair of Electr. Eng. & Comput. Syst., RWTH Aachen Univ., Germany ; Gemmeke, T. ; Noll, T.G.

The paper presents a high performance turbo decoder. Its major building blocks, the maximum-a-posteriori decoder and the interleaver, are optimized from architecture to layout level to achieve high-throughput at low-power. This includes a novel architecture for parallel interleaving, that sustains any interleaving scheme. Moreover, the key features of the major building blocks are analyzed and modeled for quick design space exploration e.g. achieving 760 Mb/s at 570 mW in a 0.13 μm-CMOS-technology. Finally, the characterized implementations are benchmarked.

Published in:

Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on  (Volume:5 )

Date of Conference:

18-23 March 2005

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