The design of RS decoder with a small core for portable communication

A new VLSI architecture using free discrepancy Berlekamp-Massey (FDBM) algorithm is proposed for wireless applications. Firstly, this project uses the FDBM algorithm to reduce the path delay. A method of module reuse is applied to reduce the overall core size successfully. Using single system clock, it is easy to integrate the core into SoC. As a result, this RS decoder has reduced core size and performs in low power with simple system integration.