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A 3-ps dead-zone double-edge-checking phase-frequency-detector with 4.78 GHz operating frequencies

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3 Author(s)
Chien-Ping Chou ; Dept. of Electr. Eng., Nat. Changhua Univ. of Educ., Taiwan ; Zhi-Ming Lin ; Jun-Da Chen

This work proposes a double-edge-checking phase frequency detector (dec-PFD), designed in 0.35-μm CMOS process with 3-V supply voltage. Consisting of four-states without feedback paths, the dec-PFD can avoid Up and DOWN signals from rising to high at the same time and thus solve current mismatch problem with 3-ps dead-zone in the phase detection. The maximum operating frequency of the PFD is 4.78 GHz. Simulated results are presented to demonstrate the capability of phase detection of the circuit.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:2 )

Date of Conference:

6-9 Dec. 2004